Wintegra Targets Carrier Transport Applications

Austin, TX, January 26, 2009. Building on its success in Wireless Infrastructure, Wintegra announces its first platform dedicated to Carrier Transport applications that include essential support for the emulation of up to 336 T1/E1 circuits with independent clock domains.  Wintegra extends its lead with market leading solutions enabling even higher channel density designs.

The fast deployment of Carrier Ethernet and MPLS networks requires means of transporting SONET and SDH data using pseudo-wires.  This can be achieved in two ways, either using one pseudo-wire for each Synchronous Payload Envelope / Virtual Container (like STS-3c or STS-12c), as described in RFC4842 (Synchronous Optical Network/Synchronous Digital Hierarchy Circuit Emulation over Packet), or by using multiple pseudo-wires that each transport one T1 or E1,  using SAToP (Structure-Agnostic Time Division Multiplexing over Packet), as suggested in RFC 4553, RFC 5086, Y.1413 and Metro Ethernet Forum Technical Specification 8 (MEF 8).

The second method, implemented by Wintegra, has the advantage that the packet network can implement an implicit Add-Drop Multiplexer functionality, where individual T1 or E1 circuits can be easily inserted or removed in the Synchronous Payload Envelope / Virtual Containers, by switching them in the packet domain. With the first method, to achieve this, it is necessary to interwork from packet to SONET/SDH, use an Add-Drop multiplexer and then interwork back to packet.

However, the second method is also more challenging to implement, since each T1/E1 can have an independent clock. The need for independent clocks comes from applications where customers lease one or more T1/E1 lines and use asynchronous clock sources to drive the T1/E1 line clocks. In some cases, as an example when the T1/E1 lines are used for Wireless Backhaul, many lines can share the same clock source, since many of them can be connected to the same Radio Network Controller.  However in other cases, like Enterprise Access, it is possible for each T1/E1 line to be leased by a different user and hence have an asynchronous clock.

For this reason, and to simplify the management of the SONET/SDH to packet interworking function by not having to define different clock domains, it is necessary to support as many as 336 Differential Clock recovery domains for an OC12 interface.

The functionality described above, including the newly released support for 336 differential clock domains, is available as part of the Multi-Service Access Platform that includes PMC-Sierra's PM8310 TEMUX® 336 framer solution plus the UFE3 (Universal Front End- an FPGA used for high channel density designs) and WinPath2 access processor from Wintegra. PMC-Sierra's TEMUX 336 features best-in-class clock control and jitter performance as well as a Scalable Bandwidth Interconnect system interface that provides independent timing information on a per T1/E1 basis across all 336 channels, which is critical in enabling circuit emulation applications.  This platform also enables a fully channelized OC3/OC12 application running any service over any port, including PWE3 (Pseudo Wire End to End Emulation), MC/ML-PPP (Multi-Class Multi-Link PPP), IMA (Inverse Multiplexing over ATM), and MFR (Multilink Frame Relay).

This third generation platform is being used by leading equipment manufacturers to design systems used for Wireless Backhaul and Optical Transport. For more information please do not hesitate to contact Us on 01727 791000 or email: wintegra@broadband.uk.com